1. Field of the Invention
The present invention relates to a method of manufacturing an isolation structure for an integrated circuit device. More particularly, the present invention relates to a method of manufacturing a shallow trench isolation structure for an integrated circuit device.
2. Description of the Related Art
Shallow trench isolation uses an anisotropic etching process to form a trench in the semiconductor substrate and subsequently, filling in the trench with a chemical in order to form a field isolation region technique of the device. Since the field isolation region formed by the shallow trench isolation process has the advantages of scalability, as well as being able to prevent the disadvantageous bird""s beak encroachment, therefore, in terms of the sub-micron CMOS process, this is a relatively ideal isolation technique.
FIGS. 1A to 1F are flow chart diagrams in cross-sectional view, illustrating a method of manufacturing shallow trench isolation region in the prior art.
Referring to FIG. 1A, first, using thermal oxidation, a pad oxide 102 is formed on a silicon substrate 100. A silicon nitride mask layer 104 is formed on the pad oxide 102, and a conventional technique is used to define the mask layer 104 and the pad oxide 102, thereby defining the isolation region of the device.
Next, referring to FIG. 1B, using a conventional technique, a photoresist (not illustrated) is formed on the surface of the silicon nitride mask layer. Also, the silicon nitride mask layer 104, pad oxide 102 and silicon substrate 100 are successively etched, thereby forming a trench 106 within the silicon substrate 100. Thereafter, the photoresist is removed.
Referring to FIG. 1C, using chemical vapor deposition (CVD), an insulation layer 112 is filled into the silicon substrate exposed by the trench 106.
Referring to FIG. 1D, using the silicon nitride mask layer 104 as the polishing stop layer, using chemical mechanical polishing (CMP) to remove the excess insulation layer 112 above the silicon nitride mask layer 104, thereby leaving behind the insulation layer 114 within the trench 106.
Subsequently, referring to FIG. 1E, a wet etching procedure is used to remove the mask layer 104. Due to the factor of isotropic etching, the insulation layer 114 covered by the edges of the trench 106 vertex results in the creation of a depression 11, and leaves behind the insulation layer 114a. 
Referring to FIG. 1F, the pad oxide layer 102 is removed by using a wet etching procedure. Conventionally, the insulation layer 114a is made of a silicon oxide material. Since the etching characteristics of the material and the etching characteristics of the pad oxide layer 102 are similar, therefore, during the removal process of the pad oxide layer, a portion of the insulation layer will also be etched away, thereby forming insulation layer 114b. 
Due to the factor of isotropic etching, the above-described depression 11 will become more serious and form an even deeper and wider depression 13. The depression 13 exposes the trench 106 vertex, causing a xe2x80x9ckink effectxe2x80x9d of the subthreshold voltage on the surface of the NMOS that is formed, an effect that increases leakage during threshold conditions.
The invention provides a shallow trench isolation manufacturing method. A T-shaped insulation layer is formed on the shallow trench and on a portion of the pad oxide layer, wherein the T-shaped insulation layer can prevent the trench vertex from being exposed during the wet etching procedure, preventing the device from the occurrence of a kink effect.
As embodied and broadly described herein, the invention provides a shallow trench isolation manufacturing method. The manufacturing method comprises forming a pad oxide layer on the substrate, and forming a mask layer on the pad oxide layer. Next, using a photoresist with opening patterns as a mask, the mask layer and the pad oxide layer are etched, and a trench is formed in the substrate. Thereafter, the photoresist is laterally etched, in order to expand the photoresist opening. Next, the mask layer exposed by the photoresist opening is etched, thereby forming a wide opening within the mask layer. Subsequently, the photoresist is removed, thereby exposing the T-shaped opening constructed by the trench and the wide opening of the mask layer. An insulation layer is formed on the upper portion of the mask layer, within the wide opening and inside the trench. Next, using the mask layer as a polishing stop layer to perform a CMP process, a portion of the insulation layer is removed, thereby exposing the mask layer and creating an even surface. Next, the mask and a portion of the pad layer are removed, thereby forming a T-shaped shallow trench isolation structure.
According to the descriptions of the present embodiment, the insulation layer formed by the above-described method covers the edges of the trench vertex. Therefore, in the successive removal of the mask layer and the pad layer during the wet tching procedure, the insulation layer covering the edges of the trench vertices can rotect the trench vertices, so that it is not exposed due to the factor of isotropic etching. Hence, the present invention can prevent the kink effect from occurring.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.